432 lines
33 KiB
C
432 lines
33 KiB
C
/* This file is auto-generated. Don't edit. */
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#ifndef NASM_IFLAGGEN_H
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#define NASM_IFLAGGEN_H 1
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#define IF_SM0 0 /* Size match operand 0 */
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#define IF_SM1 1 /* Size match operand 1 */
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#define IF_SM2 2 /* Size match operand 2 */
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#define IF_SM3 3 /* Size match operand 3 */
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#define IF_SM4 4 /* Size match operand 4 */
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#define IF_AR0 5 /* SB, SW, SD applies to operand 0 */
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#define IF_AR1 6 /* SB, SW, SD applies to operand 1 */
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#define IF_AR2 7 /* SB, SW, SD applies to operand 2 */
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#define IF_AR3 8 /* SB, SW, SD applies to operand 3 */
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#define IF_AR4 9 /* SB, SW, SD applies to operand 4 */
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#define IF_SB 10 /* Unsized operands can't be non-byte */
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#define IF_SW 11 /* Unsized operands can't be non-word */
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#define IF_SD 12 /* Unsized operands can't be non-dword */
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#define IF_SQ 13 /* Unsized operands can't be non-qword */
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#define IF_ST 14 /* Unsized operands can't be non-tword */
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#define IF_SO 15 /* Unsized operands can't be non-oword */
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#define IF_SY 16 /* Unsized operands can't be non-yword */
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#define IF_SZ 17 /* Unsized operands can't be non-zword */
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#define IF_NWSIZE 18 /* Operand size defaults to 64 in 64-bit mode */
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#define IF_OSIZE 19 /* Unsized operands must match the operand size */
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#define IF_ASIZE 20 /* Unsized operands must match the address size */
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#define IF_ANYSIZE 21 /* Ignore operand size even if explicit */
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#define IF_SX 22 /* Unsized operands not allowed */
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#define IF_SDWORD 23 /* Strict sdword64 matching */
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#define IF_PSEUDO 24 /* Pseudo-instruction (directive) */
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#define IF_JMP_RELAX 25 /* Relaxable jump instruction */
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#define IF_JCC_HINT 26 /* Hintable jump instruction */
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#define IF_OPT 27 /* Optimizing assembly only */
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#define IF_LATEVEX 28 /* Only if EVEX instructions are disabled */
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#define IF_NOREX 29 /* Instruction does not support REX encoding */
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#define IF_NOAPX 30 /* Instruction does not support APX registers or REX2 */
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#define IF_NF 31 /* Instruction supports the {nf} prefix */
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#define IF_NF_R 32 /* Instruction requires the {nf} prefix */
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#define IF_NF_N 33 /* Instruction doesn't allow the {nf} prefix */
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#define IF_NF_E 34 /* EVEX.NF set with {nf} prefix */
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#define IF_ZU 35 /* Instruction supports the {zu} prefix */
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#define IF_ZU_R 36 /* Instruction requires the {zu} prefix */
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#define IF_ZU_E 37 /* EVEX.ND set with {zu} prefix */
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#define IF_LIG 38 /* Ignore VEX/EVEX L field */
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#define IF_WIG 39 /* Ignore VEX/EVEX W field */
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#define IF_WW 40 /* VEX/EVEX W is REX.W */
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#define IF_SIB 41 /* SIB encoding required */
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#define IF_LOCK 42 /* Lockable if operand 0 is memory */
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#define IF_LOCK1 43 /* Lockable if operand 1 is memory */
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#define IF_NOLONG 44 /* Not available in long mode */
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#define IF_LONG 45 /* Long mode */
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#define IF_NOHLE 46 /* HLE prefixes forbidden */
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#define IF_MIB 47 /* split base/index EA */
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#define IF_BND 48 /* BND (0xF2) prefix available */
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#define IF_REX2 49 /* REX2 encoding required */
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#define IF_HLE 50 /* HLE prefixed */
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#define IF_FL 51 /* Instruction modifies the flags */
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#define IF_MOPVEC 52 /* M operand is a vector */
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#define IF_SCC 53 /* EVEX[27:24] is special condition code */
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#define IF_BESTDIS 54 /* Preferred disassembly pattern */
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#define IF_DFV 55 /* Destination flag values */
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/* 55...63 reserved */
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#define IF_VEX 64 /* VEX or XOP encoded instruction */
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#define IF_EVEX 65 /* EVEX encoded instruction */
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#define IF_PRIV 66 /* Privileged instruction */
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#define IF_SMM 67 /* Only valid in SMM */
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#define IF_PROT 68 /* Protected mode only */
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#define IF_UNDOC 69 /* Undocumented */
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#define IF_FPU 70 /* FPU */
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#define IF_MMX 71 /* MMX */
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#define IF_3DNOW 72 /* 3DNow! */
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#define IF_SSE 73 /* SSE (KNI, MMX2) */
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#define IF_SSE2 74 /* SSE2 */
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#define IF_SSE3 75 /* SSE3 (PNI) */
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#define IF_VMX 76 /* VMX */
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#define IF_SSSE3 77 /* SSSE3 */
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#define IF_SSE4A 78 /* AMD SSE4a */
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#define IF_SSE41 79 /* SSE4.1 */
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#define IF_SSE42 80 /* SSE4.2 */
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#define IF_SSE5 81 /* SSE5 */
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#define IF_AVX 82 /* AVX (256-bit floating point) */
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#define IF_AVX2 83 /* AVX2 (256-bit integer) */
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#define IF_FMA 84 /* Fused multiply-add */
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#define IF_BMI1 85 /* Bit manipulation instructions 1 */
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#define IF_BMI2 86 /* Bit manipulation instructions 2 */
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#define IF_TBM 87 /* */
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#define IF_RTM 88 /* */
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#define IF_AVX512 89 /* AVX-512 */
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#define IF_AVX512F 90 /* AVX-512F (base architecture) */
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#define IF_AVX512CD 91 /* AVX-512 Conflict Detection */
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#define IF_AVX512ER 92 /* AVX-512 Exponential and Reciprocal */
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#define IF_AVX512PF 93 /* AVX-512 Prefetch */
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#define IF_MPX 94 /* MPX */
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#define IF_SHA 95 /* SHA */
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#define IF_AVX512VL 96 /* AVX-512 Vector Length Orthogonality */
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#define IF_AVX512DQ 97 /* AVX-512 Dword and Qword */
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#define IF_AVX512BW 98 /* AVX-512 Byte and Word */
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#define IF_AVX512IFMA 99 /* AVX-512 IFMA instructions */
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#define IF_AVX512VBMI 100 /* AVX-512 VBMI instructions */
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#define IF_AES 101 /* AES instructions */
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#define IF_VAES 102 /* AES AVX instructions */
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#define IF_VPCLMULQDQ 103 /* AVX Carryless Multiplication */
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#define IF_GFNI 104 /* Galois Field instructions */
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#define IF_AVX512VBMI2 105 /* AVX-512 VBMI2 instructions */
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#define IF_AVX512VNNI 106 /* AVX-512 VNNI instructions */
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#define IF_AVX512BITALG 107 /* AVX-512 Bit Algorithm instructions */
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#define IF_AVX512VPOPCNTDQ 108 /* AVX-512 VPOPCNTD/VPOPCNTQ */
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#define IF_AVX5124FMAPS 109 /* AVX-512 4-iteration multiply-add */
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#define IF_AVX5124VNNIW 110 /* AVX-512 4-iteration dot product */
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#define IF_AVX512FP16 111 /* AVX-512 FP16 instructions */
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#define IF_AVX512BMM 112 /* AVX-512 BMM instructions */
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#define IF_F16C 113 /* F16C instructions */
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#define IF_SGX 114 /* Intel Software Guard Extensions (SGX) */
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#define IF_CET 115 /* Intel Control-Flow Enforcement Technology (CET) */
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#define IF_ENQCMD 116 /* Enqueue command instructions */
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#define IF_TSXLDTRK 117 /* TSX suspend load address tracking */
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#define IF_AVX512BF16 118 /* AVX-512 bfloat16 */
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#define IF_AVX512VP2INTERSECT 119 /* AVX-512 VP2INTERSECT instructions */
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#define IF_AMXTILE 120 /* AMX tile configuration instructions */
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#define IF_AMXBF16 121 /* AMX bfloat16 multiplication */
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#define IF_AMXFP16 122 /* AMX FP16 multiplication */
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#define IF_AMXFP8 123 /* AMX FP8 instructions */
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#define IF_AMXTF32 124 /* AMX TF32 multiplication */
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#define IF_AMXINT8 125 /* AMX 8-bit integer multiplication */
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#define IF_AMXCOMPLEX 126 /* AMX float16 complex multiplication */
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#define IF_AMXAVX512 127 /* EVEX zmm<-tmm conversion instructions */
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#define IF_AMXMOVRS 128 /* AMX loads with MOVRS hint */
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#define IF_AMXTRANSPOSE 129 /* AMX transpose instructions */
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#define IF_FRED 130 /* Flexible Return and Exception Delivery (FRED) */
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#define IF_RAOINT 131 /* Remote atomic operations (RAO-INT) */
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#define IF_UINTR 132 /* User interrupts */
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#define IF_CMPCCXADD 133 /* CMPccXADD instructions */
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#define IF_PREFETCHI 134 /* PREFETCHI0 and PREFETCHI1 */
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#define IF_MSRLIST 135 /* RDMSRLIST and WRMSRLIST */
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#define IF_AVXNECONVERT 136 /* AVX exceptionless floating-point conversions */
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#define IF_AVXVNNI 137 /* AVX Vector Neural Network instructions */
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#define IF_AVXVNNIINT8 138 /* AVX Vector Neural Network 8-bit integer instructions */
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#define IF_AVXVNNIINT16 139 /* AVX Vector Neural Network 16-bit integer instructions */
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#define IF_AVXIFMA 140 /* AVX integer multiply and add */
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#define IF_HRESET 141 /* History reset */
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#define IF_SMAP 142 /* Supervisor Mode Access Prevention (SMAP) */
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#define IF_SHA512 143 /* SHA512 instructions */
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#define IF_HSM3 144 /* SM3 hash instructions */
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#define IF_HSM4 145 /* SM4 hash instructions */
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#define IF_APX 146 /* Advanced Performance Extensions (APX) */
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#define IF_AVX10_1 147 /* AVX 10.1 instructions */
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#define IF_AVX10_2 148 /* AVX 10.2 instructions */
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#define IF_AVX10_VNNIINT 149 /* AVX Vector Neural Network integer instructions */
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#define IF_ADX 150 /* ADCX and ADOX instructions */
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#define IF_PKU 151 /* Protection key for user mode */
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#define IF_MONITOR 152 /* MONITOR and MWAIT */
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#define IF_MONITORX 153 /* MONITORX and MWAITX */
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#define IF_WAITPKG 154 /* User wait instruction package */
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#define IF_MSR_IMM 155 /* Immediate RDMSR/WRMSRNS instructions */
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#define IF_AESKLE 156 /* AES key locker */
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#define IF_AESKLEWIDE_KL 157 /* AES wide key locker */
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#define IF_INVPCID 158 /* INVPCID instruction */
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#define IF_PREFETCHWT1 159 /* PREFETCHWT1 instruction */
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#define IF_PBNDKB 160 /* PBNDKB instruction */
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#define IF_PCONFIG 161 /* PCONFIG instruction */
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#define IF_WBNOINVD 162 /* WBNOINVD instruction */
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#define IF_SERIALIZE 163 /* SERIALIZE instruction */
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#define IF_LKGS 164 /* LKGS instruction */
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#define IF_WRMSRNS 165 /* WRMSRNS instruction */
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#define IF_CLFLUSHOPT 166 /* CLFLUSHOPT instruction */
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#define IF_CLWB 167 /* CLWB instruction */
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#define IF_RDRAND 168 /* RDRAND instruction */
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#define IF_RDSEED 169 /* RDSEED instruction */
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#define IF_RDPID 170 /* RDPID instruction */
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#define IF_LZCNT 171 /* LZCNT instruction */
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#define IF_PTWRITE 172 /* PTWRITE instruction */
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#define IF_CLDEMOTE 173 /* CLDEMOTE instruction */
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#define IF_MOVDIRI 174 /* MOVDIRI instruction */
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#define IF_MOVDIR64B 175 /* MOVDIR64B instruction */
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#define IF_CLZERO 176 /* CLZERO instruction */
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#define IF_MOVBE 177 /* MOVBE instruction */
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#define IF_MOVRS 178 /* MOVRS instruction */
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#define IF_OBSOLETE 179 /* Instruction removed from architecture */
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#define IF_NEVER 180 /* Instruction never implemented */
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#define IF_NOP 181 /* Instruction is always a (nonintentional) NOP */
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/* 181...191 reserved */
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#define IF_8086 192 /* 8086 */
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#define IF_186 193 /* 186+ */
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#define IF_286 194 /* 286+ */
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#define IF_386 195 /* 386+ */
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#define IF_486 196 /* 486+ */
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#define IF_PENT 197 /* Pentium */
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#define IF_P6 198 /* P6 */
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#define IF_KATMAI 199 /* Katmai */
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#define IF_WILLAMETTE 200 /* Willamette */
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#define IF_PRESCOTT 201 /* Prescott */
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#define IF_IA64 202 /* IA64 (in x86 mode) */
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#define IF_X86_64 203 /* x86-64 (long or legacy mode) */
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#define IF_NEHALEM 204 /* Nehalem */
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#define IF_WESTMERE 205 /* Westmere */
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#define IF_SANDYBRIDGE 206 /* Sandy Bridge */
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#define IF_FUTURE 207 /* Ivy Bridge or newer */
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#define IF_DEFAULT 208 /* Default CPU level */
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#define IF_ANY 209 /* Allow any known instruction */
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#define IF_CYRIX 210 /* Cyrix-specific */
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#define IF_AMD 211 /* AMD-specific */
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/* 211...223 reserved */
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/* Mask bits for field 0 : 0...31 */
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#define IFM_SM0 UINT32_C(0x00000001) /* 0 */
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#define IFM_SM1 UINT32_C(0x00000002) /* 1 */
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#define IFM_SM2 UINT32_C(0x00000004) /* 2 */
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#define IFM_SM3 UINT32_C(0x00000008) /* 3 */
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#define IFM_SM4 UINT32_C(0x00000010) /* 4 */
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#define IFM_AR0 UINT32_C(0x00000020) /* 5 */
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#define IFM_AR1 UINT32_C(0x00000040) /* 6 */
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#define IFM_AR2 UINT32_C(0x00000080) /* 7 */
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#define IFM_AR3 UINT32_C(0x00000100) /* 8 */
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#define IFM_AR4 UINT32_C(0x00000200) /* 9 */
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#define IFM_SB UINT32_C(0x00000400) /* 10 */
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#define IFM_SW UINT32_C(0x00000800) /* 11 */
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#define IFM_SD UINT32_C(0x00001000) /* 12 */
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#define IFM_SQ UINT32_C(0x00002000) /* 13 */
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#define IFM_ST UINT32_C(0x00004000) /* 14 */
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#define IFM_SO UINT32_C(0x00008000) /* 15 */
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#define IFM_SY UINT32_C(0x00010000) /* 16 */
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#define IFM_SZ UINT32_C(0x00020000) /* 17 */
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#define IFM_NWSIZE UINT32_C(0x00040000) /* 18 */
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#define IFM_OSIZE UINT32_C(0x00080000) /* 19 */
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#define IFM_ASIZE UINT32_C(0x00100000) /* 20 */
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#define IFM_ANYSIZE UINT32_C(0x00200000) /* 21 */
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#define IFM_SX UINT32_C(0x00400000) /* 22 */
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#define IFM_SDWORD UINT32_C(0x00800000) /* 23 */
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#define IFM_PSEUDO UINT32_C(0x01000000) /* 24 */
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#define IFM_JMP_RELAX UINT32_C(0x02000000) /* 25 */
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#define IFM_JCC_HINT UINT32_C(0x04000000) /* 26 */
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#define IFM_OPT UINT32_C(0x08000000) /* 27 */
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#define IFM_LATEVEX UINT32_C(0x10000000) /* 28 */
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#define IFM_NOREX UINT32_C(0x20000000) /* 29 */
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#define IFM_NOAPX UINT32_C(0x40000000) /* 30 */
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#define IFM_NF UINT32_C(0x80000000) /* 31 */
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/* Mask bits for field 1 : 32...63 */
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#define IFM_NF_R UINT32_C(0x00000001) /* 32 */
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#define IFM_NF_N UINT32_C(0x00000002) /* 33 */
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#define IFM_NF_E UINT32_C(0x00000004) /* 34 */
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#define IFM_ZU UINT32_C(0x00000008) /* 35 */
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#define IFM_ZU_R UINT32_C(0x00000010) /* 36 */
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#define IFM_ZU_E UINT32_C(0x00000020) /* 37 */
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#define IFM_LIG UINT32_C(0x00000040) /* 38 */
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#define IFM_WIG UINT32_C(0x00000080) /* 39 */
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#define IFM_WW UINT32_C(0x00000100) /* 40 */
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#define IFM_SIB UINT32_C(0x00000200) /* 41 */
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#define IFM_LOCK UINT32_C(0x00000400) /* 42 */
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#define IFM_LOCK1 UINT32_C(0x00000800) /* 43 */
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#define IFM_NOLONG UINT32_C(0x00001000) /* 44 */
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#define IFM_LONG UINT32_C(0x00002000) /* 45 */
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#define IFM_NOHLE UINT32_C(0x00004000) /* 46 */
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#define IFM_MIB UINT32_C(0x00008000) /* 47 */
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#define IFM_BND UINT32_C(0x00010000) /* 48 */
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#define IFM_REX2 UINT32_C(0x00020000) /* 49 */
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#define IFM_HLE UINT32_C(0x00040000) /* 50 */
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#define IFM_FL UINT32_C(0x00080000) /* 51 */
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#define IFM_MOPVEC UINT32_C(0x00100000) /* 52 */
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#define IFM_SCC UINT32_C(0x00200000) /* 53 */
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#define IFM_BESTDIS UINT32_C(0x00400000) /* 54 */
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#define IFM_DFV UINT32_C(0x00800000) /* 55 */
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/* Mask bits for field 2 : 64...95 */
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#define IFM_VEX UINT32_C(0x00000001) /* 64 */
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#define IFM_EVEX UINT32_C(0x00000002) /* 65 */
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#define IFM_PRIV UINT32_C(0x00000004) /* 66 */
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#define IFM_SMM UINT32_C(0x00000008) /* 67 */
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#define IFM_PROT UINT32_C(0x00000010) /* 68 */
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#define IFM_UNDOC UINT32_C(0x00000020) /* 69 */
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#define IFM_FPU UINT32_C(0x00000040) /* 70 */
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#define IFM_MMX UINT32_C(0x00000080) /* 71 */
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#define IFM_3DNOW UINT32_C(0x00000100) /* 72 */
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#define IFM_SSE UINT32_C(0x00000200) /* 73 */
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#define IFM_SSE2 UINT32_C(0x00000400) /* 74 */
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#define IFM_SSE3 UINT32_C(0x00000800) /* 75 */
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#define IFM_VMX UINT32_C(0x00001000) /* 76 */
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#define IFM_SSSE3 UINT32_C(0x00002000) /* 77 */
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#define IFM_SSE4A UINT32_C(0x00004000) /* 78 */
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#define IFM_SSE41 UINT32_C(0x00008000) /* 79 */
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#define IFM_SSE42 UINT32_C(0x00010000) /* 80 */
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#define IFM_SSE5 UINT32_C(0x00020000) /* 81 */
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#define IFM_AVX UINT32_C(0x00040000) /* 82 */
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#define IFM_AVX2 UINT32_C(0x00080000) /* 83 */
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#define IFM_FMA UINT32_C(0x00100000) /* 84 */
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#define IFM_BMI1 UINT32_C(0x00200000) /* 85 */
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#define IFM_BMI2 UINT32_C(0x00400000) /* 86 */
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#define IFM_TBM UINT32_C(0x00800000) /* 87 */
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#define IFM_RTM UINT32_C(0x01000000) /* 88 */
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#define IFM_AVX512 UINT32_C(0x02000000) /* 89 */
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#define IFM_AVX512F UINT32_C(0x04000000) /* 90 */
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#define IFM_AVX512CD UINT32_C(0x08000000) /* 91 */
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#define IFM_AVX512ER UINT32_C(0x10000000) /* 92 */
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#define IFM_AVX512PF UINT32_C(0x20000000) /* 93 */
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#define IFM_MPX UINT32_C(0x40000000) /* 94 */
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#define IFM_SHA UINT32_C(0x80000000) /* 95 */
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/* Mask bits for field 3 : 96...127 */
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#define IFM_AVX512VL UINT32_C(0x00000001) /* 96 */
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#define IFM_AVX512DQ UINT32_C(0x00000002) /* 97 */
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#define IFM_AVX512BW UINT32_C(0x00000004) /* 98 */
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#define IFM_AVX512IFMA UINT32_C(0x00000008) /* 99 */
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#define IFM_AVX512VBMI UINT32_C(0x00000010) /* 100 */
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#define IFM_AES UINT32_C(0x00000020) /* 101 */
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#define IFM_VAES UINT32_C(0x00000040) /* 102 */
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#define IFM_VPCLMULQDQ UINT32_C(0x00000080) /* 103 */
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#define IFM_GFNI UINT32_C(0x00000100) /* 104 */
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#define IFM_AVX512VBMI2 UINT32_C(0x00000200) /* 105 */
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#define IFM_AVX512VNNI UINT32_C(0x00000400) /* 106 */
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#define IFM_AVX512BITALG UINT32_C(0x00000800) /* 107 */
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#define IFM_AVX512VPOPCNTDQ UINT32_C(0x00001000) /* 108 */
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#define IFM_AVX5124FMAPS UINT32_C(0x00002000) /* 109 */
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#define IFM_AVX5124VNNIW UINT32_C(0x00004000) /* 110 */
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#define IFM_AVX512FP16 UINT32_C(0x00008000) /* 111 */
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#define IFM_AVX512BMM UINT32_C(0x00010000) /* 112 */
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#define IFM_F16C UINT32_C(0x00020000) /* 113 */
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#define IFM_SGX UINT32_C(0x00040000) /* 114 */
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#define IFM_CET UINT32_C(0x00080000) /* 115 */
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#define IFM_ENQCMD UINT32_C(0x00100000) /* 116 */
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#define IFM_TSXLDTRK UINT32_C(0x00200000) /* 117 */
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#define IFM_AVX512BF16 UINT32_C(0x00400000) /* 118 */
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#define IFM_AVX512VP2INTERSECT UINT32_C(0x00800000) /* 119 */
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#define IFM_AMXTILE UINT32_C(0x01000000) /* 120 */
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#define IFM_AMXBF16 UINT32_C(0x02000000) /* 121 */
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#define IFM_AMXFP16 UINT32_C(0x04000000) /* 122 */
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#define IFM_AMXFP8 UINT32_C(0x08000000) /* 123 */
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#define IFM_AMXTF32 UINT32_C(0x10000000) /* 124 */
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#define IFM_AMXINT8 UINT32_C(0x20000000) /* 125 */
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#define IFM_AMXCOMPLEX UINT32_C(0x40000000) /* 126 */
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#define IFM_AMXAVX512 UINT32_C(0x80000000) /* 127 */
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/* Mask bits for field 4 : 128...159 */
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#define IFM_AMXMOVRS UINT32_C(0x00000001) /* 128 */
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#define IFM_AMXTRANSPOSE UINT32_C(0x00000002) /* 129 */
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#define IFM_FRED UINT32_C(0x00000004) /* 130 */
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#define IFM_RAOINT UINT32_C(0x00000008) /* 131 */
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#define IFM_UINTR UINT32_C(0x00000010) /* 132 */
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#define IFM_CMPCCXADD UINT32_C(0x00000020) /* 133 */
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#define IFM_PREFETCHI UINT32_C(0x00000040) /* 134 */
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#define IFM_MSRLIST UINT32_C(0x00000080) /* 135 */
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#define IFM_AVXNECONVERT UINT32_C(0x00000100) /* 136 */
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#define IFM_AVXVNNI UINT32_C(0x00000200) /* 137 */
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#define IFM_AVXVNNIINT8 UINT32_C(0x00000400) /* 138 */
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#define IFM_AVXVNNIINT16 UINT32_C(0x00000800) /* 139 */
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#define IFM_AVXIFMA UINT32_C(0x00001000) /* 140 */
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#define IFM_HRESET UINT32_C(0x00002000) /* 141 */
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#define IFM_SMAP UINT32_C(0x00004000) /* 142 */
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#define IFM_SHA512 UINT32_C(0x00008000) /* 143 */
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#define IFM_HSM3 UINT32_C(0x00010000) /* 144 */
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#define IFM_HSM4 UINT32_C(0x00020000) /* 145 */
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#define IFM_APX UINT32_C(0x00040000) /* 146 */
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#define IFM_AVX10_1 UINT32_C(0x00080000) /* 147 */
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#define IFM_AVX10_2 UINT32_C(0x00100000) /* 148 */
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#define IFM_AVX10_VNNIINT UINT32_C(0x00200000) /* 149 */
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#define IFM_ADX UINT32_C(0x00400000) /* 150 */
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#define IFM_PKU UINT32_C(0x00800000) /* 151 */
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#define IFM_MONITOR UINT32_C(0x01000000) /* 152 */
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#define IFM_MONITORX UINT32_C(0x02000000) /* 153 */
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#define IFM_WAITPKG UINT32_C(0x04000000) /* 154 */
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#define IFM_MSR_IMM UINT32_C(0x08000000) /* 155 */
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#define IFM_AESKLE UINT32_C(0x10000000) /* 156 */
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#define IFM_AESKLEWIDE_KL UINT32_C(0x20000000) /* 157 */
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#define IFM_INVPCID UINT32_C(0x40000000) /* 158 */
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#define IFM_PREFETCHWT1 UINT32_C(0x80000000) /* 159 */
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/* Mask bits for field 5 : 160...191 */
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#define IFM_PBNDKB UINT32_C(0x00000001) /* 160 */
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#define IFM_PCONFIG UINT32_C(0x00000002) /* 161 */
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#define IFM_WBNOINVD UINT32_C(0x00000004) /* 162 */
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#define IFM_SERIALIZE UINT32_C(0x00000008) /* 163 */
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#define IFM_LKGS UINT32_C(0x00000010) /* 164 */
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#define IFM_WRMSRNS UINT32_C(0x00000020) /* 165 */
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#define IFM_CLFLUSHOPT UINT32_C(0x00000040) /* 166 */
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#define IFM_CLWB UINT32_C(0x00000080) /* 167 */
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#define IFM_RDRAND UINT32_C(0x00000100) /* 168 */
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#define IFM_RDSEED UINT32_C(0x00000200) /* 169 */
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#define IFM_RDPID UINT32_C(0x00000400) /* 170 */
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#define IFM_LZCNT UINT32_C(0x00000800) /* 171 */
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#define IFM_PTWRITE UINT32_C(0x00001000) /* 172 */
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#define IFM_CLDEMOTE UINT32_C(0x00002000) /* 173 */
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#define IFM_MOVDIRI UINT32_C(0x00004000) /* 174 */
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#define IFM_MOVDIR64B UINT32_C(0x00008000) /* 175 */
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#define IFM_CLZERO UINT32_C(0x00010000) /* 176 */
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#define IFM_MOVBE UINT32_C(0x00020000) /* 177 */
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#define IFM_MOVRS UINT32_C(0x00040000) /* 178 */
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#define IFM_OBSOLETE UINT32_C(0x00080000) /* 179 */
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#define IFM_NEVER UINT32_C(0x00100000) /* 180 */
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#define IFM_NOP UINT32_C(0x00200000) /* 181 */
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/* Mask bits for field 6 : 192...223 */
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#define IFM_8086 UINT32_C(0x00000001) /* 192 */
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#define IFM_186 UINT32_C(0x00000002) /* 193 */
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#define IFM_286 UINT32_C(0x00000004) /* 194 */
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#define IFM_386 UINT32_C(0x00000008) /* 195 */
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#define IFM_486 UINT32_C(0x00000010) /* 196 */
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#define IFM_PENT UINT32_C(0x00000020) /* 197 */
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#define IFM_P6 UINT32_C(0x00000040) /* 198 */
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#define IFM_KATMAI UINT32_C(0x00000080) /* 199 */
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#define IFM_WILLAMETTE UINT32_C(0x00000100) /* 200 */
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#define IFM_PRESCOTT UINT32_C(0x00000200) /* 201 */
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#define IFM_IA64 UINT32_C(0x00000400) /* 202 */
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#define IFM_X86_64 UINT32_C(0x00000800) /* 203 */
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#define IFM_NEHALEM UINT32_C(0x00001000) /* 204 */
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#define IFM_WESTMERE UINT32_C(0x00002000) /* 205 */
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#define IFM_SANDYBRIDGE UINT32_C(0x00004000) /* 206 */
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#define IFM_FUTURE UINT32_C(0x00008000) /* 207 */
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#define IFM_DEFAULT UINT32_C(0x00010000) /* 208 */
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#define IFM_ANY UINT32_C(0x00020000) /* 209 */
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#define IFM_CYRIX UINT32_C(0x00040000) /* 210 */
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#define IFM_AMD UINT32_C(0x00080000) /* 211 */
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/* IF_SM0 (0) ... IF_DFV (55) */
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#define IF_IGEN_FIRST 0
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#define IF_IGEN_COUNT 56
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#define IF_IGEN_FIELD 0
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#define IF_IGEN_NFIELDS 2
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/* IF_VEX (64) ... IF_NOP (181) */
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#define IF_FEATURE_FIRST 64
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#define IF_FEATURE_COUNT 118
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#define IF_FEATURE_FIELD 2
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#define IF_FEATURE_NFIELDS 4
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/* IF_8086 (192) ... IF_AMD (211) */
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#define IF_CPU_FIRST 192
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#define IF_CPU_COUNT 20
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#define IF_CPU_FIELD 6
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#define IF_CPU_NFIELDS 1
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#define IF_FIELD_COUNT 7
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typedef struct {
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uint32_t field[IF_FIELD_COUNT];
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} iflag_t;
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/* All combinations of instruction flags used in instruction patterns */
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extern const iflag_t insns_flags[655];
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#endif /* NASM_IFLAGGEN_H */
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