474 lines
12 KiB
Python
474 lines
12 KiB
Python
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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"""
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Кодировщик инструкций фиксированного размера для КВС
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Инструкции, не зависящие от сложной адресации памяти.
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Вынесены из kvs_pass2_encoder.py для упрощения поддержки.
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"""
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import struct
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from kvs_data import INSTRUCTIONS, REGISTERS, get_reg_info
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# ========== MOV регистр-регистр ==========
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def encode_mov_reg_reg(operands):
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"""
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MOV reg, reg - переместить данные между регистрами
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Формат: переместить <регистр_назначения>, <регистр_источник>
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"""
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code = bytearray()
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instr = INSTRUCTIONS["переместить"]
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dst_info = get_reg_info(operands[0])
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src_info = get_reg_info(operands[1])
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dst = dst_info["index"]
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src = src_info["index"]
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size = dst_info["size"]
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use_66 = (size == 16)
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use_rex_w = (size == 64)
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rex = 0x40
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if use_rex_w:
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rex |= 0x08
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if src >= 8:
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rex |= 0x04
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if dst >= 8:
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rex |= 0x01
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if dst_info.get("high8") or src_info.get("high8"):
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rex = 0
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if use_66:
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code.append(0x66)
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if rex != 0x40 or use_rex_w:
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code.append(rex)
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code.extend(instr["opcode"][-1:])
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modrm = 0xC0 | ((src & 7) << 3) | (dst & 7)
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code.append(modrm)
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return code
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# ========== MOV reg8, imm8 ==========
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def encode_mov_reg8_imm8(operands):
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"""
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MOV reg8, imm8 - загрузить непосредственный байт в 8-битный регистр
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Формат: загрузить_байт <регистр8>, <байт>
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"""
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code = bytearray()
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reg_info = get_reg_info(operands[0])
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reg = reg_info["index"]
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imm = int(operands[1]) if operands[1].isdigit() else int(operands[1], 16)
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if reg_info.get("high8"):
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code.append(0xB0 + reg + 4)
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else:
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if reg < 4:
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code.append(0xB0 + reg)
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else:
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rex = 0x40
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if reg >= 8:
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rex |= 0x01
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code.append(rex)
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code.append(0xB0 + (reg & 7))
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code.append(imm & 0xFF)
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return code
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# ========== CMP/TEST регистр-регистр ==========
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def encode_cmp_reg_reg(mnemonic, operands):
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"""
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CMP reg, reg - сравнить регистры
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Формат: сравнить <регистр1>, <регистр2>
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Также TEST через проверить.
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"""
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code = bytearray()
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instr = INSTRUCTIONS[mnemonic]
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dst_info = get_reg_info(operands[0])
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src_info = get_reg_info(operands[1])
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dst = dst_info["index"]
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src = src_info["index"]
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size = dst_info["size"]
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use_66 = (size == 16)
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use_rex_w = (size == 64)
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rex = 0x40
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if use_rex_w:
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rex |= 0x08
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if src >= 8:
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rex |= 0x04
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if dst >= 8:
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rex |= 0x01
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if dst_info.get("high8") or src_info.get("high8"):
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rex = 0
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if use_66:
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code.append(0x66)
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if rex != 0x40 or use_rex_w:
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code.append(rex)
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code.extend(instr["opcode"][-1:])
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modrm = 0xC0 | ((src & 7) << 3) | (dst & 7)
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code.append(modrm)
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return code
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# ========== ADD/SUB регистр-регистр ==========
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def encode_add_sub_reg_reg(mnemonic, operands):
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"""
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ADD/SUB reg, reg - сложить/вычесть регистры
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Формат: прибавить / вычесть <регистр_назначения>, <регистр_источник>
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"""
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code = bytearray()
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instr = INSTRUCTIONS[mnemonic]
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dst_info = get_reg_info(operands[0])
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src_info = get_reg_info(operands[1])
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dst = dst_info["index"]
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src = src_info["index"]
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size = dst_info["size"]
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use_66 = (size == 16)
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use_rex_w = (size == 64)
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rex = 0x40
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if use_rex_w:
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rex |= 0x08
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if src >= 8:
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rex |= 0x04
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if dst >= 8:
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rex |= 0x01
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if dst_info.get("high8") or src_info.get("high8"):
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rex = 0
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if use_66:
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code.append(0x66)
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if rex != 0x40 or use_rex_w:
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code.append(rex)
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code.extend(instr["opcode"][-1:])
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modrm = 0xC0 | ((src & 7) << 3) | (dst & 7)
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code.append(modrm)
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return code
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# ========== MUL/IMUL/DIV/IDIV ==========
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def encode_muldiv(mnemonic):
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"""
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MUL/IMUL/DIV/IDIV - умножение и деление (работают с RAX/RDX)
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Формат: умножить / умножить_знаковое / разделить / разделить_знаковое
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"""
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code = bytearray()
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instr = INSTRUCTIONS[mnemonic]
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subop = instr["subop"]
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code.append(0x48)
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code.extend(instr["opcode"])
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modrm = 0xC0 | (subop << 3) | 0
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code.append(modrm)
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return code
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# ========== AND/OR/XOR регистр-регистр ==========
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def encode_and_or_xor_reg_reg(mnemonic, operands):
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"""
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AND/OR/XOR reg, reg - логические операции над регистрами
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"""
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code = bytearray()
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instr = INSTRUCTIONS[mnemonic]
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dst_info = get_reg_info(operands[0])
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src_info = get_reg_info(operands[1])
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dst = dst_info["index"]
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src = src_info["index"]
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size = dst_info["size"]
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use_66 = (size == 16)
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use_rex_w = (size == 64)
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rex = 0x40
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if use_rex_w:
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rex |= 0x08
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if src >= 8:
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rex |= 0x04
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if dst >= 8:
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rex |= 0x01
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if dst_info.get("high8") or src_info.get("high8"):
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rex = 0
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if use_66:
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code.append(0x66)
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if rex != 0x40 or use_rex_w:
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code.append(rex)
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code.extend(instr["opcode"][-1:])
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modrm = 0xC0 | ((src & 7) << 3) | (dst & 7)
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code.append(modrm)
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return code
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# ========== NOT/NEG ==========
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def encode_not_neg(mnemonic, operands):
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"""
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NOT/NEG - инвертировать/отрицать регистр
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"""
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code = bytearray()
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instr = INSTRUCTIONS[mnemonic]
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reg_info = get_reg_info(operands[0])
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reg = reg_info["index"]
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size = reg_info["size"]
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subop = instr["subop"]
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if size == 64:
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code.append(0x48)
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elif size == 16:
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code.append(0x66)
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if reg >= 8:
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code.append(0x41)
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code.extend(instr["opcode"])
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modrm = 0xC0 | (subop << 3) | (reg & 7)
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code.append(modrm)
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return code
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# ========== INC/DEC ==========
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def encode_incdec(mnemonic, operands):
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"""
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INC / DEC - инкремент и декремент регистра
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"""
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code = bytearray()
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instr = INSTRUCTIONS[mnemonic]
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reg_info = get_reg_info(operands[0])
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reg = reg_info["index"]
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size = reg_info["size"]
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subop = instr["subop"]
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if size == 64:
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rex = 0x48
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if reg >= 8:
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rex |= 0x01
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code.append(rex)
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code.append(0xFF)
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elif size == 32:
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rex = 0x40
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if reg >= 8:
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rex |= 0x01
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if rex != 0x40:
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code.append(rex)
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code.append(0xFF)
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elif size == 16:
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code.append(0x66)
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rex = 0x40
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if reg >= 8:
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rex |= 0x01
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if rex != 0x40:
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code.append(rex)
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code.append(0xFF)
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elif size == 8:
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if reg_info.get("high8"):
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code.append(0xFE)
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else:
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if reg < 4:
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code.append(0xFE)
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else:
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rex = 0x40
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if reg >= 8:
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rex |= 0x01
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code.append(rex)
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code.append(0xFE)
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modrm = 0xC0 | (subop << 3) | (reg & 7)
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code.append(modrm)
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return bytes(code)
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modrm = 0xC0 | (subop << 3) | (reg & 7)
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code.append(modrm)
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return bytes(code)
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# ========== Стек (PUSH/POP) ==========
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def encode_push_reg(operands):
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"""PUSH reg"""
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code = bytearray()
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reg_info = get_reg_info(operands[0])
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reg = reg_info["index"]
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size = reg_info["size"]
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if size == 64:
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if reg < 8:
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code.append(0x50 + reg)
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else:
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code.append(0x41)
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code.append(0x50 + (reg - 8))
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elif size == 16:
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code.append(0x66)
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if reg < 8:
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code.append(0x50 + reg)
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else:
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code.append(0x41)
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code.append(0x50 + (reg - 8))
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else:
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raise ValueError(f"PUSH не поддерживает {size}-битные регистры")
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return code
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def encode_pop_reg(operands):
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"""POP reg"""
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code = bytearray()
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reg_info = get_reg_info(operands[0])
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reg = reg_info["index"]
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size = reg_info["size"]
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if size == 64:
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if reg < 8:
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code.append(0x58 + reg)
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else:
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code.append(0x41)
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code.append(0x58 + (reg - 8))
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elif size == 16:
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code.append(0x66)
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if reg < 8:
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code.append(0x58 + reg)
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else:
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code.append(0x41)
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code.append(0x58 + (reg - 8))
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else:
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raise ValueError(f"POP не поддерживает {size}-битные регистры")
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return code
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def encode_push_imm(operands):
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"""PUSH imm"""
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code = bytearray()
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imm = int(operands[0]) if operands[0].isdigit() else int(operands[0], 16)
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if -128 <= imm <= 127:
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code.append(0x6A)
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code.append(imm & 0xFF)
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else:
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code.append(0x68)
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code.extend(struct.pack('<i', imm))
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return code
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# ========== Сдвиги и вращения ==========
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def encode_shift_rotate(mnemonic, operands):
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"""
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SHL/SHR/SAR/ROL/ROR - сдвиги и вращения
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"""
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code = bytearray()
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reg_info = get_reg_info(operands[0])
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|||
|
|
reg = reg_info["index"]
|
|||
|
|
size = reg_info["size"]
|
|||
|
|
shift = int(operands[1]) if operands[1].isdigit() else int(operands[1], 16)
|
|||
|
|
|
|||
|
|
if size == 64:
|
|||
|
|
code.append(0x48)
|
|||
|
|
|
|||
|
|
code.append(0xC1)
|
|||
|
|
|
|||
|
|
subop_map = {
|
|||
|
|
"сдвиг_влево": 4,
|
|||
|
|
"сдвиг_вправо": 5,
|
|||
|
|
"сдвиг_арифметический_вправо": 7,
|
|||
|
|
"вращать_влево": 0,
|
|||
|
|
"вращать_вправо": 1,
|
|||
|
|
}
|
|||
|
|
subop = subop_map.get(mnemonic, 0)
|
|||
|
|
|
|||
|
|
modrm = 0xC0 | (subop << 3) | (reg & 7)
|
|||
|
|
code.append(modrm)
|
|||
|
|
code.append(shift & 0xFF)
|
|||
|
|
|
|||
|
|
return bytes(code)
|
|||
|
|
|
|||
|
|
|
|||
|
|
# ========== Системные и отладочные ==========
|
|||
|
|
|
|||
|
|
def encode_syscall():
|
|||
|
|
return INSTRUCTIONS["вызов_системы"]["opcode"]
|
|||
|
|
|
|||
|
|
def encode_int(operands):
|
|||
|
|
code = bytearray()
|
|||
|
|
instr = INSTRUCTIONS["прервать"]
|
|||
|
|
code.extend(instr["opcode"])
|
|||
|
|
imm = int(operands[0]) if operands[0].isdigit() else int(operands[0], 16)
|
|||
|
|
code.append(imm & 0xFF)
|
|||
|
|
return code
|
|||
|
|
|
|||
|
|
def encode_hlt():
|
|||
|
|
return INSTRUCTIONS["остановить"]["opcode"]
|
|||
|
|
|
|||
|
|
def encode_int3():
|
|||
|
|
return INSTRUCTIONS["отладка"]["opcode"]
|
|||
|
|
|
|||
|
|
def encode_nop():
|
|||
|
|
return INSTRUCTIONS["нет_операции"]["opcode"]
|
|||
|
|
|
|||
|
|
|
|||
|
|
# ========== Инструкции работы с флагами ==========
|
|||
|
|
|
|||
|
|
def encode_flag_instruction(mnemonic):
|
|||
|
|
return INSTRUCTIONS[mnemonic]["opcode"]
|
|||
|
|
|
|||
|
|
|
|||
|
|
# ========== Ввод-вывод ==========
|
|||
|
|
|
|||
|
|
def encode_in(operands):
|
|||
|
|
code = bytearray()
|
|||
|
|
instr = INSTRUCTIONS["ввод_байта"]
|
|||
|
|
code.extend(instr["opcode"])
|
|||
|
|
port = int(operands[0]) if operands[0].isdigit() else int(operands[0], 16)
|
|||
|
|
code.append(port & 0xFF)
|
|||
|
|
return code
|
|||
|
|
|
|||
|
|
def encode_out(operands):
|
|||
|
|
code = bytearray()
|
|||
|
|
instr = INSTRUCTIONS["вывод_байта"]
|
|||
|
|
code.extend(instr["opcode"])
|
|||
|
|
port = int(operands[0]) if operands[0].isdigit() else int(operands[0], 16)
|
|||
|
|
code.append(port & 0xFF)
|
|||
|
|
return code
|
|||
|
|
|
|||
|
|
|
|||
|
|
# ========== Строковые инструкции ==========
|
|||
|
|
|
|||
|
|
def encode_string_instruction(mnemonic):
|
|||
|
|
return INSTRUCTIONS[mnemonic]["opcode"]
|
|||
|
|
|
|||
|
|
|
|||
|
|
# ========== Идентификация процессора ==========
|
|||
|
|
|
|||
|
|
def encode_cpuid():
|
|||
|
|
return INSTRUCTIONS["идентифицировать_процессор"]["opcode"]
|
|||
|
|
|
|||
|
|
def encode_rdtsc():
|
|||
|
|
return INSTRUCTIONS["прочитать_счётчик"]["opcode"]
|
|||
|
|
|
|||
|
|
|
|||
|
|
# ========== XCHG ==========
|
|||
|
|
|
|||
|
|
def encode_xchg(operands):
|
|||
|
|
"""XCHG reg, reg - обменять регистры"""
|
|||
|
|
code = bytearray()
|
|||
|
|
instr = INSTRUCTIONS["обменять"]
|
|||
|
|
reg1_info = get_reg_info(operands[0])
|
|||
|
|
reg2_info = get_reg_info(operands[1])
|
|||
|
|
reg1 = reg1_info["index"]
|
|||
|
|
reg2 = reg2_info["index"]
|
|||
|
|
|
|||
|
|
rex = 0x48 if reg1_info["size"] == 64 else 0x40
|
|||
|
|
if reg1 >= 8 or reg2 >= 8:
|
|||
|
|
rex |= 0x01
|
|||
|
|
if reg2 >= 8:
|
|||
|
|
rex |= 0x04
|
|||
|
|
code.append(rex)
|
|||
|
|
code.extend(instr["opcode"])
|
|||
|
|
modrm = 0xC0 | ((reg2 & 7) << 3) | (reg1 & 7)
|
|||
|
|
code.append(modrm)
|
|||
|
|
return code
|